1. Field of the Invention
The invention relates to a solid-state image sensor, and more particularly to an active type XY addressable solid-state image sensor having compatibility with a process of fabricating CMOS transistor.
2. Description of the Related Art
Conventional solid-state image sensors can be grouped into MOS type and CCD type in accordance with a transfer layer for transferring signal charges generated by photoelectric transfer. In particular, CCD type solid-state image sensor has been widely used for VTR integrally including a camera, a digital camera, a fax machine and so on, and is presently being developed for enhancement in performances.
Some solid-state image sensors have compatibility with a process of fabricating CMOS transistor (hereinafter, such solid-state image sensors are referred to simply as "CMOS sensor"), as described in Nikkei Micro Device, Vol. 7, 1997, pp. 120-125. CMOS sensor has advantages that it can operate with a single power source such as a 5V or 3.3V cell with the result of low power consumption, that it can be fabricated in conventional CMOS fabrication process, and that peripheral circuits such as a signal processing circuit can be mounted on a common chip.
FIGS. 1 and 2 are cross-sectional views of a basic cell in CMOS sensor. FIG. 1 also illustrates a photoelectric transfer section in which electric charges are being accumulated, and FIG. 2 also illustrates a photoelectric transfer section from which electric charges have been reset.
With reference to FIG. 1, a basic cell of CMOS sensor is comprised of a p-type semiconductor substrate 101, a p-type well layer 102 formed in the semiconductor substrate 101 and partially exposed at a surface of the p-type semiconductor substrate 101, p+ semiconductor regions 103a and 103b exposed at a surface of the p-type semiconductor substrate 101, and isolating a region from adjacent regions in each of which a semiconductor device is fabricated, a first n+ semiconductor region 104 sandwiched between the p-type well 102 and the p+ semiconductor region 103a, a second n+ semiconductor region 105 sandwiched between the p-type well 102 and the p+ semiconductor region 103b, a control MOSFET 201 having a gate electrode in facing relation to a part of the p-type well 102 appearing at a surface of the p-type semiconductor substrate 101, a first MOSFET 202 acting as a source follower amplifier, and a second MOSFET 203 acting as a horizontal selection switch.
The basic cell of CMOS sensor is electrically connected to an external circuit through the second MOSFET 203.
The external circuit is comprised of at third MOSFET 204 acting as a load of the source follower amplifier 202, a fourth MOSFET 205 for transferring dark output, a fifth MOSFET 206 for transferring bright output, a first capacitor 207 electrically connected to a source or drain of the fourth MOSFET 205 for accumulating dark output therein, and a second capacitor 208 electrically connected to a source or drain of the fifth MOSFET 206 for accumulating bright output therein.
The first n+ semiconductor region 104 acts as a photoelectric transfer section for converting lights into electric charges. The first n+ semiconductor region 104 is electrically connected to a gate of the first MOSFET 202. The second n+ semiconductor region 105 acts as a drain of the control MOSFET 201.
The first, second and third MOSFETs 202, 203 and 204 are connected in series with one another between voltages VSS and VDD. One of sources and drains of the fifth and sixth MOSFETs 205 and 206 are electrically connected to a node located between the second and third MOSFETs 203 and 204, and the others are electrically connected both to the first and second capacitors 207 and 208, respectively, and output terminals.
The p+ semiconductor regions 103a and 103b are grounded. The second n+ semiconductor region 105 is in electrical connection with a source voltage VDD.
A plurality of such basic cells as illustrated in FIGS. 1 and 2 are arranged in a matrix to thereby define CMOS cell rows, as partially illustrated in FIG. 3A. Each of the basic cells 50 is electrically connected to vertical registers 51, a horizontal register 52, a load transistor 54, and an output line 53.
The load transistor 54 corresponds to the third load MOSFET 204 illustrated in FIGS. 1 and 2.
The output line 53 is electrically connected to the fourth and fifth MOSFETs 205 and 206, and the first and second capacitors 207 and 208 through MOSFET 55 acting as a vertical switch selected by the horizontal register 52.
FIG. 3B is a circuit diagram of CMOS sensor. Parts or elements that correspond to those in FIGS. 1 and 2 have been provided with the same reference numerals. A control pulse .phi.R is applied to a gate of the control MOSFET 201. An address signal X is applied to a gate of the second MOSFET 203 acting as a horizontal selection switch. The load transistor 54 and the output line 53 are electrically connected to a source of the second MOSFET 203.
Hereinbelow is explained an operation of CMOS sensor illustrated in FIGS. 1, 2, 3A and 3B.
First, as illustrated in FIG. 2, the control pulse .phi.R of the control MOSFET 201 is set equal to a high level voltage to thereby set the first n+ semiconductor region 104 equal to the source voltage VDD.
Then, as illustrated in FIG. 1, the control pulse .phi.R of the control MOSFET 201 is set equal to a low level voltage for prevention of blooming.
The first n+ semiconductor region 104 acting as a photoelectric transfer section generates electrons and holes, based on lights incidents thereto. The thus generated electrons are accumulated in a depletion layer, and the thus generated holes are discharged through the p-type well 102.
In FIGS. 1 and 2, a hatched area having a deeper potential than the source voltage VDD is not depleted.
Then, a potential of the first n+ semiconductor region or photoelectric transfer section 104 is varied in accordance with the number of accumulated electrons. The variation in the potential of the first n+ semiconductor region or photoelectric transfer section 104 is output into the second MOSFET 203 acting as a horizontal selection switch through a source of the first MOSFET 202 acting as a source follower amplifier by virtue of source follower operation of the first MOSFET 202. Thus, there is obtained photoelectric transfer characteristics having superior linearity.
There is generated kTC noise caused by reset operation in the first n+ semiconductor region or photoelectric transfer section 104. However, such kTC noise can be removed by sampling and accumulating dark output generated prior to transfer of signal electric charges, and calculating a difference between bright output and the thus accumulated dark output.
In the above-mentioned solid-state image sensor having compatibility with CMOS fabrication process, a potential in the first n+ semiconductor region or photoelectric transfer section 104 varies in accordance with the accumulated electrons, and the variation in the potential is output into the second MOSFET or horizontal selection switch 203 through a source of the first MOSFET or source follower amplifier 202.
Herein, there is a relation among an amount Q of signal electric charges, a parasitic capacity C of the first n+ semiconductor region or photoelectric transfer section 104, and an output voltage V, as follows.
V=Q/C
FIG. 4 illustrates a relation between an amount of incident lights and a potential, and an output voltage.
In general, as illustrated in FIG. 4, an output voltage is in proportion to an amount of incident light or a potential. However, the solid-state image sensor having compatibility with CMOS fabrication process, as illustrated in FIGS. 1 and 2, is accompanied with a problem as follows. Since a photoelectric transfer section is formed of the first n+ semiconductor region 104, it is unavoidable for a parasitic capacity C of the photoelectric transfer section 104 to become high. As a result, it is not possible to produce high potential variation V caused by signal electric charges. This causes a problem of reduction in an output transfer efficiency.
There have been suggested many solid-state image sensors.
For instance, Japanese Unexamined Patent Publication No. 63-13582 has suggested a solid-state image sensor comprising a pixel array including pixel cells arranged in a matrix, each pixel cell having a photoelectric transfer device and a switching device for selecting a certain photoelectric transfer device, and a switching MOSFET receiving a vertical signal transmitted from the pixel array, and transmitting the received vertical signal to an output line. A bias voltage is applied to a well region where the pixel array is formed, in order to absorb false signals therein. A back bias voltage is applied to a well region of the switching MOSFET in order to reduce a junction capacity between the well region and a semiconductor region defining the switching MOSFET.
Japanese Unexamined Patent Publication No. 8-241982 has suggested a solid-state image sensor in which a p-type well and an n-type semiconductor layer are formed in a self-alignment manner to thereby make a region around the p-type well and the n-type semiconductor layer depleted. As a result, a parasitic capacity can be reduced in a region around the junction.
Japanese Unexamined Patent Publication No. 9-260628 has suggested a solid-state image sensor comprising an n-type semiconductor substrate, a p-type well region formed at a surface of the semiconductor substrate, heavily doped n-type regions formed in the vicinity of the p-type well region, and a lightly doped n-type region between and around the heavily doped n-type regions. A region around the heavily doped n-type regions, and the lightly doped n-type region are depleted by putting pn junction between the heavily doped n-type regions and the p-type well region in reverse-biased condition.
However, since a photoelectric transfer section is formed from a heavily doped n-type semiconductor region in all of the above-mentioned Japanese Unexamined Patent Publications. Hence, these Publications are also accompanied with such a problem as mentioned earlier that a great parasitic capacity of a photoelectric transfer section reduces an output transfer efficiency.